vga port companion circuit PACVGA200 ?2010 scillc. all rights reserved. publication order number: may 2010 rev. 2 PACVGA200/d features ? single chip solution for the vga port interface ? includes esd protection, level shifting, and rgb termination ? seven channels of esd protection for all vga port connector pins meeting iec-61000-4-2 level-4 esd requirements ( 8kv contact discharge) ? very low loading capacitance from esd protection diodes on video lines, 4pf typical ? 75 termination resistors for video lines (matched to 1% typ.) ? ttl to cmos level-translating buffers with power down mode for hsync and vsync lines ? bi-directional level shifting n-channel fets provided for ddc_clk & ddc_data channels ? compact 24-pin qsop package ? lead-free version available applications ? notebook computers with vga port ? desktop pcs with vga port product description the PACVGA200 incorporates seven channels of esd protection for all signal lines commonly found in a vga port. esd protection is implemented with current steering diodes designed to safely handle the high surge currents encount ered with iec-61000-4-2 level-4 esd protection ( 8kv contact discharge). when a channel is subjected to an electrostatic discharge, the esd current pulse is diverted via the protection diodes into either the positive supply rail or ground where it may be safely dissipated. separate positive supply rails are provided for the video, ddc and sync channels to facilitate interfacing with low voltage video controller ics and provide design flexibility in multi-supply-voltage environments. two non-inverting drivers provide buffering for the hsync and vsync signals from the video controller ic (sync_in1, sync_in2). these buffers accept ttl input levels and convert them to cmos output levels that swing between ground and v cc 4 . these drivers have nominal 60 output impedance (r s ) to match the characteristic impedance of the hsync & vsync lines of the video cables typically used in pc applications. two n-channel fets provide the level shifting function required when the ddc controller is operated at a lower supply voltage than the monitor. three 75 termination resistors suitable for terminating the video signals from the video dac are also provided. these resistors have separate input pins to allow insertion of additional emi filtering, if required, between the termination point and the esd protection diodes. these resistors are matched to better than 2% for excellent signal level matching for the r/g/b signals. when the pwr_up input is driven low, the sync inputs can be floated without causing the sync buffers to draw any current from the v cc 4 supply. when the pwr_up input is low, the sync outputs are driven low. an internal diode (d1 in schematic on previous page) is also provided so that v cc 3 can be derived from v cc 4, if desired, by connecting v cc 3 to v_bias. in applications where v cc 4 may be powered down, diode d1 blocks any dc current paths from the ddc_out pins back to the powered down v cc 4 rail via the top esd protection diodes. the PACVGA200 device is housed in a 24-pin qsop package and is available with optional lead-free finishing.
PACVGA200 rev. 2 | page 2 of 10 | www.onsemi.com simplified electrical schematic video_1 video_2 video_3 3 4 5 2 6 v cc 1 gndd gndd 75 75 75 gnda 8 9 10 term_1 term_2 term_3 gnda 7 r c v cc 2 ddc_in2 17 gndd gndd gndd v cc 3 18 ddc_out2 r c v cc 2 ddc_in1 16 gndd gndd gndd v cc 3 15 ddc_out1 12 14 gndd r b 19 gndd sync_in1 gndd v cc 4 23 sd1 v_bias sync_out1 pwr_up 1 13 20 11 r c gndd 21 gndd sync_in2 v cc 4 1 24 sd2 gndd sync_out2 22 r s r s d1 to p view 24-pin qsop 1 2 3 4 5 6 7 8 16 15 14 13 17 18 9 10 20 19 21 22 11 12 23 24 video_3 gndd gnda term_1 term_2 term_3 pwr_up v cc 2 v cc 4 v cc 1 video_1 video_2 sd1 sync_out2 sync_in2 sync_out1 sync_in1 ddc_out2 ddc_in2 ddc_in1 ddc_out1 v cc 3 v_bias sd2
PACVGA200 rev. 2 | page 3 of 10 | www.onsemi.com ordering information part numbering information lead-free finish pins package ordering part number 1 part marking 24 qsop-24 PACVGA200qr PACVGA200qr note 1: parts are shipped in tape & reel form unless otherwise specified. pin descriptions lead(s) name description 1 v cc 4 positive voltage supply pin. this is an isolated v cc pin for the sync_1, sync_2, sd1 and sd2 circuits. 2 v cc 1 positive voltage supply pin. this is an isolated v cc pin for the video_1, video_2 and video_3 esd circuits. 3-5 video_1, video_2, video_3 rgb video protection channels. these pins ti e to the rgb video lines (for example, the blue signal) between the vga cont roller device and the video connector. 6 gndd digital ground reference supply pin. 7 gnda ground reference supply pin for term_1, term_2 and term_3 pins. 8-10 term_1, term_2, term_3 rgb video termination channels. these pins tie to the rgb video lines (for example, the blue signal) providing a 75 termination to gnda for the given video channel. 11 pwr_up sync signal output 1. ties to the video connector side of one of the sync lines (for example the horizontal sync signal). 12 v cc 2 positive voltage supply pin. this is an isolated v cc pin for the ddc_in1 and ddc_in2 input circuits. defines the logic one level for the ddc_outn outputs. 13 v_bias used to derive v cc3 from v cc4 input. 14 v cc 3 positive voltage supply pin. this is an isolated v cc pin for the ddc_out1 and ddc_out2 esd protection circuits. 15 ddc_out1 ddc signal output 1. connects to t he connector side of one of the ddc signals (for example, the bidirectional ddc_data serial line). 16 ddc_in1 ddc signal input 1. connects to the vg a controller side of one of the ddc signals (for example, the bidirectional ddc_data serial line). 17 ddc_in2 ddc signal input 2. connects to the vg a controller side of one of the ddc signals (for example, the bidirectional ddc_clk).
PACVGA200 rev. 2 | page 4 of 10 | www.onsemi.com lead(s) name description 18 ddc_out2 ddc signal output 2. connects to t he connector side of one of the ddc signals (for example, the bidirectional ddc_clk). 19 sync_in1 sync signal buffer input 1. connects to the vga controller side of one of the sync lines (for example, the horizontal sync signal). 20 sync_out1 sync signal buffer output 1. connec ts to the video connector side of one of the sync lines (for example the horizontal sync signal). 21 sync_in2 sync signal buffer input 2. connects to the vga controller side of one of the sync lines (for example, the vertical sync signal). 22 sync_out2 sync signal buffer output 2. connec ts to the video connector side of one of the sync lines (for example the vertical sync signal). 23 sd1 sync signal filter 1. connects to the video connector side of one of the sync lines (for example the vertical sync signal). 24 sd2 sync signal filter 2. connects to the video connector side of one of the sync lines (for example the horizontal sync signal). specifications absolute maximum ratings parameter rating units v cc 1,v cc 2,v cc 3, and v cc 4 supply voltage [gnd - 0.5] to +6.0 v diode d1 forward dc current 100 a storage temperature range -65 to +150 c dc voltage at inputs video_1, video_2, video_3 term_1, term_2, term_3 ddc_in1, ddc_in2 ddc_out1, ddc_out2 sync_in1, sync_in2 (gnd - 0.5) to (v cc 1 + 0.5) -6.0, +6.0 (gnd - 0.5) to (v cc 2 + 0.5) (gnd - 0.5) to (v cc 3 + 0.5) (gnd - 0.5) to (v cc 4 + 0.5) v v v v v package power rating 1000 mw standard operating conditions parameter rating units operating temperature range 0 to +70 c
PACVGA200 rev. 2 | page 5 of 10 | www.onsemi.com electrical operat ing characteristics (see note 1) symbol parameter conditions min typ max units i cc1 v cc 1 supply current v cc 1 = 5.0v, video inputs at v cc 1 or gnd level 10 a i cc2 , i cc3 v cc 2 & v cc 3 supply current v cc 2 = v cc 3 = 5.0v 10 a v cc 4 = 5.0v; sync inputs at gnd or v cc 4 level; pwr-up pin at v cc 4; sync outputs unloaded 10 a v cc 4 = 5.0v; sync inputs at 3.0v; pwr-up pin at v cc 4; sync outputs unloaded 200 a i cc4 v cc 4 supply current v cc 4 = 5.0v; pwr-up input at gnd; sync outputs unloaded 10 a v bias v bias open circuit voltage no external current drawn from v bias pin v cc 4-0.8 v video termination resistance 71.25 75 78.75 r t r t resistance matching 1 2 % v ih logic high input voltage v cc 4 = 5.0v; see note 2 2.0 v v il logic low input voltage v cc 4 = 5.0v; see note 2 0.8 v v oh logic high output voltage i oh = -4ma, v cc 4 = 5.0v; see note 2 4.5 4.8 v v ol logic low output voltage i ol = 4ma, v cc 4 = 5.0v; see note 2 0.18 0.32 v r oh 50 125 r ol output resistance see note 2 45 80 r b ,r p resistor value pwr_up = v cc 3 = 5.0v 0.5 1.0 2.0 m r c v cc 2 pull-down resistor value v cc 2 = 3.0v 0.5 1.5 3.0 m i n input current video inputs hsync, vsync inputs v cc 1= 5.0v; v in = v cc 1 or gnd v cc 4 = 5.0v; v in = v cc 4 or gnd + 1 + 1 a a i off off-state leakage current, level-shifting nfet (v cc 2 - v ddc_in ) < 0.4v; v ddc_out = v cc 2 (v cc 2 - v ddc_out ) < 0.4v; v ddc_in = v cc 2 10 10 a a
PACVGA200 rev. 2 | page 6 of 10 | www.onsemi.com symbol parameter conditions min typ max units v on voltage drop across level shifting nfet when turned on v cc 2= 2.5v; v s = gnd; i ds = 3ma 0.15 v c in input capacitance video_1,video_2 & video_3 inputs v cc 1 = 5.0v; v in = 2.5v; measured at 1mhz v cc 1 = 2.5v; v in = 1.25v; measured at 1mhz 3.0 3.0 4.0 4.5 5.0 5.6 pf pf t plh sync drivers l => h propagation delay c l = 50pf; v cc =5.0v,input t r and t f < 5ns 8.0 12.0 ns t phl sync drivers h => l propagation delay c l = 50pf; v cc =5.0v; input t r and t f < 5ns 8.0 12.0 ns t r, t f sync drivers output rise & fall times c l = 50pf; v cc =5.0v; input t r and t f < 5ns (measured 10% - 90%) 5.0 7.0 10.0 ns v esd esd withstand voltage v cc 1 = v cc 3 = v cc 4 = 5v; note 3 8 kv note 1: all parameters specified over standard ope rating conditions unless otherwise noted. note 2: this parameter applies only to the hsync and vsy nc channels. hsync and vsync have 8ma drivers with r s added in series to terminate transmission line. note 3: per the iec-61000-4-2 international esd st andard, level 4 contact discharge method. v cc 1, v cc 3 and v cc 4 must be bypassed to gnd via a low impedance ground plane with a 0.2u f, low inductance, chip ceramic capacitor at each supply pin. esd pulse is applied between the applicable pi ns and gnd. esd pulse can be positive or negative with respect to gnd. applicable pins are: video_1, video_2, video_3, sync_out1, sd1, sync_out2, sd2, ddc_out1 and ddc_out2. all other pins are esd protected to the industry standard 2kv per the human body model (mil-std-883, method 3015).
PACVGA200 rev. 2 | page 7 of 10 | www.onsemi.com test circuit information average current through v cc 4 (i cc 4) the circuit in figure 1 was used to characterize i cc 4 current as sync_in signal frequency varies. a square wave signal was connected to the input of one of the syn c buffers (i.e. pin 19 or pin 21). the frequency of this signal was varied between 0 and 100 khz. the risetime and falltime was kept constant at 10ns. three different values of c1 were used: 0pf, 50pf and 100pf. the results are plotted in figure 2 . 0v v cc 4 +5v sync_in i cc 4 c1 sync_out 3.3v figure 1. sync buffer i cc 4 test circuit figure 2. i cc 4 vs. sync_in frequency performance data
PACVGA200 rev. 2 | page 8 of 10 | www.onsemi.com application information figure 3. typical connection diagram a resistor may be necessary between the v cc 3 pin and ground if protection agai nst a stream of esd pulses is required while the PACVGA200 is in the power-down state. the value of this resistor should be chosen such that the extra charge deposited into the v cc 3 bypass capacitor by each esd pulse will be discharged before the next esd pulse occurs. the maximum esd repetition rate specified by the iec-61000-4-2 standard is one pulse per second. when the PACVGA200 is in the power-up state, an internal dischar ge resistor is connected to ground via an fet switch for this purpose. for the same reason, v cc 1 and v cc 4 may also require bypass capacitor di scharging resistors to ground if there are no other components in the system to provide a discharge path to ground. gnda, the reference voltage for the 75 resistors is not connected internally to gndd and should ideally be connected to the ground of the video dac ic.
PACVGA200 rev. 2 | page 9 of 10 | www.onsemi.com mechanical details qsop mechanical specifications: PACVGA200 devices are packaged in 24-pin qsop packages. dimensions are presented below. for complete information on the qsop-24 package, see the california micro devices qsop package information document. package dimensions package qsop (jedec name is ssop) pins 24 millimeters inches dimensions min max min max a 1.35 1.75 0.053 0.069 a1 0.10 0.25 0.004 0.010 b 0.20 0.30 0.008 0.012 c 0.18 0.25 0.007 0.010 d 8.56 8.73 0.337 0.344 e 3.81 3.98 0.150 0.157 e 0.64 bsc 0.025 bsc h 5.79 6.19 0.228 0.244 l 0.40 1.27 0.016 0.050 # per tube 55 pcs* # per tape and reel 2500 pcs controlling dimension: inches * this is an approximate number which may vary. package dimensions for qsop-24
PACVGA200 rev. 2 | page 10 of 10 | www.onsemi.com on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes witho ut further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any parti cular purpose, nor does scillc assume any liability arising out of the application or use of any pr oduct or circuit, and specific ally disclaims any and all liability, including without li mitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or spec ifications can and do vary in different applications and actu al performance may vary over time. all operating parameters, including ?typicals? must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not de signed, intended, or authorized for use as components in systems intended for surg ical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers , employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reason able attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : orderlit@onsemi.com n. american technical support : 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81-3-5773-3850 on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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